1. Field of the Disclosure
The embodiments relate to a phase locked loop (PLL).
2. Description of the Related Art
In the field of semiconductor integrated circuit (IC) devices, technological development is in progress to achieve further enhancement of operation speeds and further reduction of power consumption. In a PLL circuit in a semiconductor IC device, reduction in noise occurring along the time axis, which is called “jitter,” is desired. In particular, in a semiconductor IC device including both analog and digital circuits, noise attributed to a digital circuit causes a PLL circuit to generate jitter.
FIG. 1 illustrates an example of a conventional PLL circuit. In the conventional PLL circuit, a frequency of a reference signal ref-CLK generated from an oscillator circuit (not shown), such as a quartz oscillator, is divided into a 1/N frequency component by a first frequency divider 1, and is then input into a phase comparator 2. An output signal of a second frequency divider 3 having a division ratio of 1/M, for example, is input as a feedback signal into the phase comparator 2. The phase comparator 2 detects a phase difference between the output signals of the first frequency divider 1 and the output signal of the second frequency divider 3, and outputs a pulse signal in accordance with the phase difference to a charge pump 4.
As shown in FIG. 1, the charge pump 4 outputs an output voltage to a low pass filter 5 (LPF), in accordance with the pulse signal output from the phase comparator 2. The output voltage of the charge pump 4 has a DC component and a pulse component from the pulse signal output from the phase comparator 2. The DC component varies in accordance with frequency variation of the pulse signal, and the pulse component varies in accordance with the pulse signal corresponding to the phase difference.
As further shown in FIG. 1, the low pass filter 5 smoothes the output voltage of the charge pump 4, and outputs an output signal with a removed high frequency component to a voltage/current converter (WI converter) 6. The V/I converter 6 converts the output voltage of the low pass filter 5 to a current, and outputs the current to a current control oscillator (ICO) 7.
As further shown in FIG. 1, the ICO 7 outputs an output signal out-CLK, having a frequency based on the output current of the V/I converter 6, to a digital circuit 8 and to the second frequency divider 3. The digital circuit 8 performs required operations in accordance with the output signal out-CLK.
The PLL circuit of FIG. 1 operates so as to conform the frequency and phase of the output signal of the second frequency divider 3 to the frequency and phase of the output signal of the first frequency divider 1.
FIG. 2 illustrates an operation in the case where the division ratio of each of the respective first and second frequency dividers 1 and 3 of FIG. 1 is 1. In accordance with the loop from the phase comparator 2 of FIG. 1 to the ICO 7 of FIG. 1, the frequency and phase of the output signal out-CLK converge, so that the reference signal ref-CLK and the output signal out-CLK are in-phase with each other.
As shown in FIG. 2, upon output of the output signal out-CLK from the ICO 7 of FIG. 1, the digital circuit 8 of FIG. 1 operates a required switching operation, in accordance with a timing of a rise and fall of the output signal out-CLK. Therefore, in accordance with the operation of the digital circuit 8, power-supply noise N, synchronous with the output signal out-CLK, is generated in a power supply Vcc potential and a ground GND potential that are supplied to the respective circuits, which are coupled between the phase comparator 2 and the ICO 7 through power supply lines.
As further shown in FIG. 2, since a comparison operation is performed in the phase comparator 2 of FIG. 1 in accordance with a timing of a rise or fall of the reference signal ref-CLK, the output signal is destabilized, due to the power-supply noise N. The output signal of the charge pump 4 of FIG. 1, operating on the common power supply with the digital circuit 8, is also destabilized.
As a consequence, as shown further in FIG. 2, a jitter Z frequently occurs during the rise and fall of the output signal out-CLK.
As one example of a related conventional technique, Laid-Open Japanese Patent Application (JP-A) No. 2005-79835 discloses a PLL circuit that includes a phase shifter interposed between a voltage control oscillator and a frequency divider to reduce jitter occurrence. However, in such a configuration, which includes the phase shifter in a feedback loop that feeds back the output signal of the voltage control oscillator to the phase comparator, the loop affects the lock-up speed until the frequency of the output signal of the voltage control oscillator is stabilized. Since the delay time caused as a result of the phase shifter has to be adjusted optimally, the phase shifter must include a delay length switching portion. Consequently, the circuit size of the phase shifter is increased.
As another example, JP-A-2006-174243 discloses a PLL circuit, in which a delay value of a delay circuit in a voltage control oscillator is controlled to enable stepwise switching of an oscillation frequency characteristic. However, a jitter reduction feature is not disclosed.
As still another example, JP-A-08-56157 discloses a PLL circuit that includes a variable delay circuit provided with a voltage control circuit. However, a jitter reduction feature is not disclosed.
Conventional PLL circuits, such as described above, are problematic at least in that, when the timing of occurrence of power-supply noise N with the output signal out-CLK and the phase comparison timing in the phase comparator 2 overlap, the jitter Z increases in the output signal out-CLK.